For some time the market of electronic products is increasingly focused on mobile devices (computers, mobile phones and personal digital assistants, for example). Batteries that have a limited availability of energy provide power needed to operate these mobile devices. Thus the need of reducing the power consumption of all the electronic components (central processing unit, memory, display, etc.) included in mobile devices arose, in order to extend the autonomy of such mobile devices with the same batteries used.
Typically, the electronic components are Systems On A Chip or SOCs, i.e., complete electronic systems integrated on a single chip of semiconductor material. In this case, the desired reduction in power consumption is achieved through a reduction in operating voltages of transistors included in the SOCs. In particular, the SRAMs included in such SOCs comprise a number of transistors which is equal to 50%-90% of the total number of transistors present on the same SOC. Considering that the power consumption of electronic components affects the total power consumption of the SOC in proportion to their number of transistors, it is clear that the reduction of the operating voltage of the SRAM memories results in a substantial reduction in the power consumption of the entire SOC.
As it is known, a random access memory or RAM is a special type of memory wherein each memory cell (capable of storing a binary data, or bits) can be directly accessed with the same access time. In particular, a SRAM memory does not require any refresh operation of the stored data, as it retains data values for a theoretically infinite time (at least up to a shutdown of an electronic system wherein the SRAM memory is used).
The reference memory cell in the SRAM memories (for example, commonly used in CMOS-type technology) is formed by six transistors, and therefore it is usually called “6T” memory cell. In particular, a 6T memory cell includes a bistable latch formed by two crossed logic inverters (i.e., with an input of each inverter coupled to an output of the other inverter), each of which includes two transistors. The bistable latch has two stable equilibrium conditions corresponding to the two possible logic values (i.e., 0 or 1) of the stored bit. Two access transistors are used to selectively access the bistable latch during a read or write operation of the corresponding memory cell.
A five-transistor memory cell called “5T” was derived from the 6T memory cell by removing one of the access transistors to the bistabile latch. The removal of such access transistor (and, therefore, also of the components for driving it) allows for a savings in area up to 20-30% compared to the 6T memory cell, while its power consumption is substantially halved.
Unfortunately, the reduction of the operating voltages of the transistors may generate serious problems related to the reliability of the memory cell. Indeed, at a low operating voltage it is much more difficult, if not impossible, to force the switching of the transistors for writing the memory cell (as the operating voltage may be not sufficient to overcome a threshold voltage of the transistors required for their switching).
However, the required circuits specifications for a reliable writing (i.e., able to properly write the wanted bit in the memory cell) are opposed to the circuits specifications needed to achieve a stable reading (i.e., a reading that does not change the bit stored in the read memory cell) and to obtain a stable standby condition (i.e., where no changes occur in the bit stored upon time). In more detail, for achieving a correct writing, the access transistors should be very conductive to force the bistable latch to change its equilibrium condition, while for ensuring a stable reading and a stable standby condition, the access transistors should have a reduced conductivity to avoid an undesired switching of the bistable latch (though this conductivity may not be kept too low so as to allow transferring the read bit). Therefore, known expedients concerning ratios between the transistor sizes or form factors of the transistors themselves may not be successfully applied; for example, optimizing the form factors of the transistors to obtain a reliable writing may result in a memory cell with low stability in reading and in standby condition and, conversely, optimizing the form factors to have a stable memory cell in reading and in the stand-by condition may result in a low reliability in writing.
In particular, the asymmetry of the 5T memory cells makes even higher the contrast between the specifications required for a stable reading and standby condition and the specifications required for a reliable writing. In order to obtain a reliable writing, it may be necessary that the access transistor of the memory cell should be very conductive while the transistors that form the logic inverters should have different conductivity from each other to compensate for the asymmetry of the memory cell. Such conductivity values are different to those required for good stability in reading and standby condition. In addition, the memory cell is more unstable when storing a determined logic value (e.g., the logic value 0) compared to when storing the other logic value. In fact, during a reading of the memory cell (which implies that the bistable latch is biased to a non-zero reading voltage through the access transistor), such reading voltage is input to the inverter to which the access transistor is coupled; therefore, in a condition of the inverter (corresponding to the logic value 0) the reading voltage tends to switch it, while in the other condition of the inverter (corresponding to the logic value 1) the reading voltage tends to maintain the same condition. A similar problem may occur in a standby condition of the memory cell, due to capacitive coupling between the inverter and the access transistor.
The problem of the stability in reading and in the standby condition may be exacerbated by the increasing size reduction (scaling) of the transistors. In this case, the transistors are much more sensitive to changes in voltage at their terminals, and this may lead to unwanted currents even for small voltage fluctuations (tenths of volt). In addition, transistors with much reduced dimensions are subject to greater fluctuations in the values of their physical parameters (due to the increased weight of aberrations in an optical lithographic technique commonly used for their formation). Therefore, transistors formed at different times and/or in different regions of the same chip may present mismatches in their physical parameters, undermining the correct and stable operation of the devices.